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april 2007 rev 4 1/56 1 m25pe16 16 mbit, low-voltage, page-era sable serial flash memory with byte-alterability, 50 mhz spi bus, standard pinout features spi bus compatible serial interface 16-mbit page-erasable flash memory page size: 256 bytes ? page write in 11 ms (typical) ? page program in 0.8 ms (typical) ? page erase in 10 ms (typical) subsector erase (4 kbytes) sector erase (64 kbytes) bulk erase (16 mbits) 2.7 v to 3.6 v single supply voltage 50 mhz clock rate (maximum) deep power-down mode 1 a (typical) electronic signature ? jedec standard two-byte signature (8015h) software write protection on a 64 kbyte sector basis hardware write protection of the memory area selected using the bp0, bp1 and bp2 bits more than 100 000 write cycles more than 20 year data retention packages ? ecopack? (rohs compliant) vfqfpn8 (mp) 6 x 5mm (mlp8) so8w (mw) 208 mils width www.st.com
contents m25pe16 2/56 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 serial data output (q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 serial data input (d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 serial clock (c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 chip select (s ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 reset (reset ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.6 write protect (w ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.7 v cc supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.8 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 spi modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1 sharing the overhead of modifying data . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2 an easy way to modify data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3 a fast way to modify data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.4 polling during a write, program or erase cycle . . . . . . . . . . . . . . . . . . . . 13 4.5 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.6 active power, standby power and deep power-down modes . . . . . . . . . 13 4.7 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.8 protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.8.1 protocol-related protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.8.2 specific hardware and software protections . . . . . . . . . . . . . . . . . . . . . 15 5 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1 write enable (wren) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.2 write disable (wrdi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.3 read identification (rdid) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
m25pe16 contents 3/56 6.4 read status register (rdsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.4.1 wip bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.4.2 wel bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.4.3 bp2, bp1, bp0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.4.4 srwd bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.5 write status register (wrsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.6 read data bytes (read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.7 read data bytes at higher speed (fast_read) . . . . . . . . . . . . . . . . . . 30 6.8 read lock register (rdlr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.9 page write (pw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.10 page program (pp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.11 write to lock register (wrlr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.12 page erase (pe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.13 sector erase (se) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.14 subsector erase (sse) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.15 bulk erase (be) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.16 deep power-down (dp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.17 release from deep power-down (rdp) . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7 power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9 initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 12 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 13 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
list of tables m25pe16 4/56 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. software protection truth table (sectors 0 to 31, 64 kbyte granularity) . . . . . . . . . . . . . . . 15 table 3. protected area sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 4. memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 5. instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 6. read identification (rdid) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 7. status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 8. protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 9. lock register out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 10. lock register in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 11. power-up timing and vwi threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 table 12. device status a fter a reset low pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 13. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 14. operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 15. ac measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 16. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 17. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 18. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 19. reset conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 20. timings after a reset low pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 21. vfqfpn8 (mlp8) 8-lead very thin fine pitch quad flat package no lead, 6 5 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 22. so8 wide ? 8 lead plastic small outline, 20 8 mils body width, mechanical data. . . . . . . . 53 table 23. ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 24. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
m25pe16 list of figures 5/56 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. vfqfpn and so connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. bus master and memory devices on the spi bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 4. spi modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 5. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 6. write enable (wren) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 7. write disable (wrdi) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 8. read identification (rdid) instruction sequence and data-out sequence . . . . . . . . . . . . . 24 figure 9. read status register (rdsr) instruction sequence and data-out sequence . . . . . . . . . . 26 figure 10. write status register (wrsr) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 11. read data bytes (read) instruction sequence and data-out sequence . . . . . . . . . . . . . . 29 figure 12. read data bytes at higher speed (fast_read) instruction sequence and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 13. read lock register (rdlr) instruction sequence and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 14. page write (pw) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 figure 15. page program (pp) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 16. write to lock register (wrlr) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 17. page erase (pe) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 figure 18. sector erase (se) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 figure 19. subsector erase (sse) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 20. bulk erase (be) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 21. deep power-down (dp) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 22. release from deep power-down (rdp) instruction sequence . . . . . . . . . . . . . . . . . . . . . . 42 figure 23. power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 24. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 25. serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 26. write protect setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 27. output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 28. reset ac waveforms while a program or erase cycle is in progress . . . . . . . . . . . . . . . . . 51 figure 29. vfqfpn8 (mlp8) 8-lead very thin dual flat package no lead, 6 5mm, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 30. so8 wide ? 8 lead plastic small outline, 208 mils body width, package outline . . . . . . . . 53
description m25pe16 6/56 1 description the m25pe16 is a 16 mbit (2 mb 8) serial paged flash memory accessed by a high speed spi-compatible bus. the memory can be written or programmed 1 to 256 bytes at a time, using the page write or page program instruction. the page write instruction consists of an integrated page erase cycle followed by a page program cycle. the memory is organized as 32 sectors that are further divided up into 16 subsectors each (512 subsectors in total). each sector cont ains 256 pages and each subsector contains 16 pages. each page is 256 bytes wide. thus, the whole memory can be viewed as consisting of 8192 pages, or 2,097,152 bytes. the memory can be erased a page at a time, using the page erase instruction, a subsector at a time, using the subsector erase instruction, a sector at a time, using the sector erase instruction, or as a whole, using the bulk erase instruction. the memory can be write protected by either hardware or software using mixed volatile and non-volatile protection features, depending on the application needs. the protection granularity is of 64 kbytes (sector granularity). in order to meet environmental requirements, st offers these devices in ecopack? packages. ecopack? packages are lead-free and rohs compliant. ecopack is an st trademark. ecopack specifications are available at: www.st.com .
m25pe16 description 7/56 figure 1. logic diagram figure 2. vfqfpn and so connections 1. there is an exposed die paddle on the underside of th e mlp8 package. this is pulled, internally, to v ss , and must not be allowed to be connected to any other voltage or signal line on the pcb. 2. see section 12: package mechanical for package dimensions, and how to identify pin-1. table 1. signal names c serial clock d serial data input q serial data output s chip select w write protect reset reset v cc supply voltage v ss ground reset ai12343c s v cc m25pe16 v ss q c d w 1 ai12344c 2 3 4 8 7 6 5 d v ss c reset q sv cc m25pe16 w
signal description m25pe16 8/56 2 signal description 2.1 serial data output (q) this output signal is used to transfer data serially out of the device. data is shifted out on the falling edge of serial clock (c). 2.2 serial data input (d) this input signal is used to transfer data serially into the device. it receives instructions, addresses, and the data to be programmed. values are latched on the rising edge of serial clock (c). 2.3 serial clock (c) this input signal provides the timing of the serial interface. instructions, addresses, or data present at serial data input (d) are latched on the rising edge of serial clock (c). data on serial data output (q) ch anges after the fa lling edge of serial clock (c). 2.4 chip select (s ) when this input signal is high, the device is deselected and serial data output (q) is at high impedance. unless an internal read, progra m, erase or write cycle is in progress, the device will be in the standby mode (this is not the deep po wer-down mode). driving chip select (s ) low selects the device, placing it in the active power mode. after power-up, a falling edge on chip select (s ) is required prior to the start of any instruction. 2.5 reset (reset ) the reset (reset ) input provides a hardware reset for the memory. when reset (reset ) is driven high, the memory is in the normal operating mode. when reset (reset ) is driven low, the memory will ente r the reset mode. in this mode, the output is high impedance. driving reset (reset ) low while an internal operation is in progress will affect this operation (write, program or erase cycle) and data may be lost. see ta bl e 1 2 for the status of the device after a reset low pulse. 2.6 write protect (w ) the write protect (w ) input is used to freeze the size of the area of memory that is protected against write, program and erase instructions (as specified by the values in the bp2, bp1 and bp0 bits of th e status register). see section 6.4: read status register (rdsr) .
m25pe16 signal description 9/56 2.7 v cc supply voltage v cc is the supply voltage. 2.8 v ss ground v ss is the reference for the v cc supply voltage.
spi modes m25pe16 10/56 3 spi modes these devices can be driven by a microcontroller with its spi peripheral running in either of the two following modes: cpol=0, cpha=0 cpol=1, cpha=1 for these two modes, input data is latched in on the rising edge of serial clock (c), and output data is available from th e falling edge of serial clock (c). the difference between the two modes, as shown in figure 4 , is the clock polarity when the bus master is in stand-by mode and not transferring data: c remains at 0 for (cpol=0, cpha=0) c remains at 1 for (cpol=1, cpha=1) figure 3. bus master and memory devices on the spi bus 1. the write protect (w ) and reset (reset ) signals should be driven, hi gh or low as appropriate. figure 4 shows an example of three devices connected to an mcu, on an spi bus. only one device is selected at a time, so only one device drives the serial data output (q) line at a time, the other devices are high impedance. the pull-up resistor r (represented in figure 4 ) ensures that no device is selected if the bus master leaves the s line in the high impedance state. in applications where the bus master might enter a state where all inputs/outputs spi lines are in high impedance at the same time (for example, if the bus master is reset during the transmission of an instruction), the clock line (c) must be connected to an external pull- down resistor so that, if all inputs/outputs become high impedance, the c line is pulled low (while the s line is pulled high). this ensures that s and c do not become high at the same time, and so, that the t shch requirement is met. ai12836c spi bus master spi memory device sdo sdi sck cqd s spi memory device cqd s spi memory device cqd s cs3 cs2 cs1 spi interface with (cpol, cpha) = (0, 0) or (1, 1) w reset w reset w reset rr r v cc v cc v cc v cc v ss v ss v ss v ss r
m25pe16 spi modes 11/56 the typical value of r is 100 k ? , assuming that the time constant r*c p (c p = parasitic capacitance of the bus line) is short enough, as the s and c lines must reach the correct state (s = high and c = low) while the spi bus is in high impedance. example: c p = 50 pf, that is r*c p = 5 s <=> the application must ensure that the bus master never leaves the spi bus in the high impedance state for a time period shorter than 5s. figure 4. spi modes supported ai01438b c msb cpha d 0 1 cpol 0 1 q c msb
operating features m25pe16 12/56 4 operating features 4.1 sharing the overhead of modifying data to write or program one (or more) data bytes, two instructions are required: write enable (wren), which is one byte, and a page write (pw) or page program (pp) sequence, which consists of four bytes plus data. this is followed by the internal cycle (of duration t pw or t pp ). to share this overhead, the page write (pw) or page program (pp) instruction allows up to 256 bytes to be programmed (changing bits from 1 to 0) or written (changing bits to 0 or 1) at a time, provided that they lie in consecutive addresses on the same page of memory. 4.2 an easy way to modify data the page write (pw) instruction provides a convenient way of modifying data (up to 256 contiguous bytes at a time), and simply requires the start address, and the new data in the instruction sequence. the page write (pw) instruction is entered by driving chip select (s ) low, and then transmitting the instruction byte, three address bytes (a23-a0) and at least one data byte, and then driving chip select (s ) high. while chip select (s ) is being held low, the data bytes are written to the data buffer, starting at the address given in the third address byte (a7-a0). when chip select (s ) is driven high, the write cycle starts. the remaining, unchanged, bytes of the data buffer are automatically loaded with the values of the corresponding bytes of the addressed memory page. the addressed memory page then automatically put into an erase cycle. finally, the addressed memory page is programmed with the contents of the data buffer. all of this buffer management is handled internally, and is transparent to the user. the user is given the facility of being able to alter the co ntents of the memory on a byte-by-byte basis. for optimized timings, it is recommended to use the page write (pw) instruction to write all consecutive targeted bytes in a single sequence versus using several page write (pw) sequences with each containing only a few bytes (see section 6.9: page write (pw) and table 18: ac characteristics ).
m25pe16 operating features 13/56 4.3 a fast way to modify data the page program (pp) instruction provides a fast way of modifying data (up to 256 contiguous bytes at a time), provided that it only involves resetting bits to 0 that had previously been set to 1. this might be: when the designer is programming the device for the first time when the designer knows that the page has already been erased by an earlier page erase (pe), subsector erase ( sse), sector erase (se) or bu lk erase (be) instruction. this is useful, for example, when storing a fast stream of data, having first performed the erase cycle when time was available when the designer knows that the only changes involve resetting bits to 0 that are still set to 1. when this method is possible, it ha s the additional advantage of minimizing the number of unnecessary erase operations, and the extra stress incurred by each page. for optimized timings, it is recommended to use the page program (pp) instruction to program all consecutive targeted bytes in a single sequence versus using several page program (pp) sequences with each containing only a few bytes (see section 6.10: page program (pp) and table 18: ac characteristics ). 4.4 polling during a write, program or erase cycle a further improvement in the time to write (p w, wrsr), program (pp) or erase (se, sse or be) can be achieved by not waiting for the worst case delay (t w , t pw , t pp , t pe , t se , t sse or t be ). the write in progress (wip) bit is provided in the status register so that the application program can monitor it s value, polling it to establis h when the previous cycle is complete. 4.5 reset an internal power-on reset circuit helps protect against inadvertent data writes. addition protection is provided by driving reset (reset ) low during the power-on process, and only driving it high when v cc has reached the correct voltage level, v cc (min). 4.6 active power, standby powe r and deep power-down modes when chip select (s ) is low, the device is selected, and in the active power mode. when chip select (s ) is high, the device is deselected, but could remain in the active power mode until all internal cycles have completed (program, erase, write). the device then goes in to the standby power mode. the device consumption drops to i cc1 . the deep power-down mode is entered when the specific instruction (the deep power- down (dp) instruction) is executed. the device consumption drops further to i cc2 . when in this mode, only the release from deep power-down instruction is accepted. all other instructions are ignored. the device remain s in the deep power- down mode until the release from deep power-down instruction is executed. this can be used as an extra software protection mechanism, when the device is not in active use, to protect the device from inadvertent write, program or erase instructions.
operating features m25pe16 14/56 4.7 status register the status register contains a number of status and control bits that can be read or set (as appropriate) by using specific instructions. see section 6.4: read status register (rdsr) for a detailed description of the status register bits. 4.8 protection modes the environments where non-volatile memory devices are used can be very noisy. no spi device can operate correctly in the presence of excessive noise. to help combat this and to meet the needs of modularized applications, the m25pe16 features the following flexible data protection mechanisms: 4.8.1 protocol-rel ated protections power on reset and an internal timer (t puw ) can provide protection against inadvertent changes while the power supply is outside the operating specification. program, erase and write instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. all instructions that modify data must be preceded by a write enable (wren) instruction to set the write enable latch (wel) bit. this bit is returned to its reset state by the following events: ?power-up ? reset (reset ) driven low ? write disable (wrdi) instruction completion ? page write (pw) instruction completion ? write status register (wrsr) instruction completion ? page program (pp) instruction completion ? write to lock register (w rlr) instruction completion ? page erase (pe) instruction completion ? subsector erase (sse) instruction completion ? sector erase (se) instruction completion ? bulk erase (be) instruction completion the reset (reset ) signal can be driven low to freeze and reset the internal logic. for the specific cases of program and wr ite cycles, the designer should refer to section 6.5: write status register (wrsr) , section 6.9: page write (pw) , section 6.10: page program (pp) , section 6.12: page erase (pe) , section 6.13: sector erase (se) and section 6.14: subsector erase (sse) , and to table 12: device status after a reset low pulse . in addition to the low power consumption feature, the deep power-down mode offers extra software protection from inadvertent write, program and erase instructions while the device is not in active use.
m25pe16 operating features 15/56 4.8.2 specific hardware and software protections there are two software protected modes, spm1 and spm2, that can be combined to protect the memory array as required. the spm2 can be hardware protected with the help of the w input pin. spm1 and spm2 the first software protected mode (spm1) is managed by specific lock registers assigned to each 64 kbyte sector. the lock registers can be read and written using the read lock register (rdlr) and write to lock register (wrlr) instructions. in each lock register two bits control the protection of each sector: the write lock bit and the lock down bit. ? write lock bit: the write lock bit determines whether the contents of the sector can be modified (using the write, program or erase instructions). when the write lock bit is set, ?1?, the sector is write protected ? any operations that attempt to change the data in the sector will fail. when the write lock bi t is reset to ?0?, t he sector is not write protected by the lock register, and may be modified. ? lock down bit: the lock down bit provides a mechanism for protecting software data from simple hacking and malicious attack. when the lock down bit is set, ?1?, further modification to the write lock and lock down bits cannot be performed. a reset, or power-up, is required before changes to these bits can be made. when the lock down bit is reset, ?0?, the write lock and lock down bits can be changed. the write lock bit and the lock down bit are volatile and their value is reset to ?0? after a power-down or a reset (see table 12: device status after a reset low pulse ). the definition of the lock register bits is given in table 9: lock register out . table 2. software protection truth table (sectors 0 to 31, 64 kbyte granularity) sector lock register protection status lock down bit write lock bit 00 sector unprotected from program/eras e/write operations, protection status reversible 01 sector protected from program/erase/ write operations, protection status reversible 10 sector unprotected from prog ram/erase/write operations, sector protection status cannot be changed except by a reset or power-up. 11 sector protected from prog ram/erase/write operations, sector protection status cannot be changed except by a reset or power-up.
operating features m25pe16 16/56 the second software protected mode (spm2) uses the block protect (bp2, bp1, bp0, see section 6.4.3 )) bits to allow part of the memory to be configured as read-only. table 3. protected area sizes status register content memory content bp2 bit bp1 bit bp0 bit protected area unprotected area 0 0 0 none all sectors (1) (32 sectors: 0 to 31) 1. the device is ready to accept a bulk erase instructi on if, and only if, all block protect (bp2, bp1, bp0) are 0. 0 0 1 upper 32nd (sector 31) lower 31st/32nd (31 sectors: 0 to 30) 0 1 0 upper sixteenth (two sectors: 30 and 31) lower 15/16ths (30 sectors: 0 to 29) 0 1 1 upper eighth (four sectors: 28 to 31) lower seven-eighths (28 sectors: 0 to 27) 1 0 0 upper quarter (eight sectors: 24 to 31) lower three-quarters (24 sectors: 0 to 23) 1 0 1 upper half (sixteen se ctors: 16 to 31) lower half (16 sectors: 0 to 15) 1 1 0 all sectors (32 sectors: 0 to 31) none 1 1 1 all sectors (32 sectors: 0 to 31) none
m25pe16 memory organization 17/56 5 memory organization the memory is organized as: 8192 pages (256 bytes each). 2,097,152 bytes (8 bits each) 32 sectors (512 kbits, 65536 bytes each) 512 subsectors (32 kbits, 4096 bytes each) each page can be individually: programmed (bits are programmed from 1 to 0) erased (bits are erased from 0 to 1) written (bits are changed to either 0 or 1) the device is page, sector or bulk erasable (bits are erased from 0 to 1). table 4. memory organization sector subsector address range sector subsector address range 31 511 1ff000h 1fffffh 23 383 17f000h 17ffffh ... ... ... ... ... ... 496 1f0000h 1f0fffh 368 170000h 170fffh 30 495 1ef000h 1effffh 22 367 16f000h 16ffffh ... ... ... ... ... ... 480 1e0000h 1e0fffh 352 160000h 160fffh 29 479 1df000h 1dffffh 21 351 15f000h 15ffffh ... ... ... ... ... ... 464 1d0000h 1d0fffh 336 150000h 150fffh 28 463 1cf000h 1cffffh 20 335 14f000h 14ffffh ... ... ... ... ... ... 448 1c0000h 1c0fffh 320 140000h 140fffh 27 447 1bf000h 1bffffh 19 319 13f000h 13ffffh ... ... ... ... ... ... 432 1b0000h 1b0fffh 304 130000h 130fffh 26 431 1af000h 1affffh 18 303 12f000h 12ffffh ... ... ... ... ... ... 416 1a0000h 1a0fffh 288 120000h 120fffh 25 415 19f000h 19ffffh 17 287 11f000h 11ffffh ... ... ... ... ... ... 400 190000h 190fffh 272 110000h 110fffh 24 399 18f000h 18ffffh 16 271 10f000h 10ffffh ... ... ... ... ... ... 384 180000h 180fffh 256 100000h 100fffh
memory organization m25pe16 18/56 15 255 ff000h fffffh 6 111 6f000h 6ffffh ... ... ... ... ... ... 240 f0000h f0fffh 96 60000h 60fffh 14 239 ef000h effffh 5 95 5f000h 5ffffh ... ... ... ... ... ... 224 e0000h e0fffh 80 50000h 50fffh 13 223 df000h dffffh 4 79 4f000h 4ffffh ... ... ... ... ... ... 208 d0000h d0fffh 64 40000h 40fffh 12 207 cf000h cffffh 3 63 3f000h 3ffffh ... ... ... ... ... ... 192 c0000h c0fffh 48 30000h 30fffh 11 191 bf000h bffffh 2 47 2f000h 2ffffh ... ... ... ... ... ... 176 b0000h b0fffh 32 20000h 20fffh 10 175 af000h affffh 1 31 1f000h 1ffffh ... ... ... 160 a0000h a0fffh 16 10000h 10fffh 9 159 9f000h 9ffffh 0 15 0f000h 0ffffh ... ... ... ... ... ... 144 90000h 90fffh 4 04000h 04fffh 8 143 8f000h 8ffffh 3 03000h 03fffh ... ... ... 2 02000h 02fffh 128 80000h 80fffh 1 01000h 01fffh 7 127 7f000h 7ffffh 0 00000h 00fffh ... ... ... 112 70000h 70fffh table 4. memory organization (continued) sector subsector address range sector subsector address range
m25pe16 memory organization 19/56 figure 5. block diagram ai12346c s w control logic high voltage generator i/o shift register address register and counter 256 byte data buffer 256 bytes (page size) x decoder y decoder c d q status register 00000h 1fffffh 000ffh reset whole memory array can be made read-only on a 64 kb basis through the lock registers size of the read-only memory area
instructions m25pe16 20/56 6 instructions all instructions, addresses and data are shifted in and out of the device, most significant bit first. serial data input (d) is sampled on the first rising edge of serial clock (c) after chip select (s ) is driven low. then, the one-byte instruction code must be shifted in to the device, most significant bit first, on serial data input (d), each bit being latched on the rising edges of serial clock (c). the instruction set is listed in ta bl e 5 . every instruction sequence starts with a one-byte instruction code. depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. in the case of a read data bytes (read), read data bytes at higher speed (fast_read), read identification (rdid), read status register (rdsr), or read lock register (rdlr) instruction, the shifted-in instruction sequence is followed by a data-out sequence. chip select (s ) can be driven high after any bit of the data-out sequence is being shifted out. in the case of a page write (pw), page program (pp), write to lock register (wrlr), page erase (pe), sector erase (se), subs ector erase (sse), bulk erase (be), write status register (wrsr), write enable (wre n), write disable (wrdi), deep power-down (dp) or release from deep power-down (rdp) instruction, chip select (s ) must be driven high exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. that is, chip select (s ) must driven high when the number of clock pulses after chip select (s ) being driven low is an exact multiple of eight. all attempts to access the memory array duri ng a write cycle, program cycle or erase cycle are ignored, and the internal write cycle, program cycle or erase cycle continues unaffected.
m25pe16 instructions 21/56 table 5. instruction set instruction description one-byte instruction code address bytes dummy bytes data bytes wren write enable 0000 0110 06h 0 0 0 wrdi write disable 0000 0100 04h 0 0 0 rdid read identification 1001 1111 9fh 0 0 1 to 3 rdsr read status register 0000 0101 05h 0 0 1 to wrsr write status register 0000 0001 01h 0 0 1 wrlr write to lock register 1110 0101 e5h 3 0 1 rdlr read lock register 1110 1000 e8h 3 0 1 read read data bytes 0000 0011 03h 3 0 1 to fast_read read data bytes at higher speed 0000 1011 0bh 3 1 1 to pw page write 0000 1010 0ah 3 0 1 to 256 pp page program 0000 0010 02h 3 0 1 to 256 pe page erase 1101 1011 dbh 3 0 0 se sector erase 1101 1000 d8h 3 0 0 sse subsector erase 0010 0000 20h 3 0 0 be bulk erase 1100 0111 c7h 0 0 0 dp deep power-down 1011 1001 b9h 0 0 0 rdp release from deep power-down 1010 1011 abh 0 0 0
instructions m25pe16 22/56 6.1 write enable (wren) the write enable (wren) instruction ( figure 6 ) sets the write enable latch (wel) bit. the write enable latch (wel) bit must be set prior to every page write (pw), page program (pp), page erase (pe), sector eras e (se), subsector erase (sse), bulk erase (be), write status register (wrsr) and write to lock register (wrlr) instructions. the write enable (wren) instruction is entered by drivin g chip select (s ) low, sending the instruction code, and then driving chip select (s ) high. figure 6. write enable (wren) instruction sequence c d ai02281e s q 2 1 34567 high impedance 0 instruction
m25pe16 instructions 23/56 6.2 write disable (wrdi) the write disable (wrdi) instruction ( figure 7 ) resets the write enable latch (wel) bit. the write disable (wrdi) instruction is entered by driving chip select (s ) low, sending the instruction code, and then driving chip select (s ) high. the write enable latch (wel) bit is reset under the following conditions: power-up write disable (wrdi) instruction completion write status register (wrsr) instruction completion page write (pw) instruction completion page program (pp) instruction completion write to lock register (w rlr) instruction completion page erase (pe) instruction completion sector erase (se) instruction completion subsector erase (sse) instruction completion bulk erase (be) instruction completion figure 7. write disable (wrdi) instruction sequence c d ai03750d s q 2 1 34567 high impedance 0 instruction
instructions m25pe16 24/56 6.3 read identification (rdid) the read identification (rdid) in struction allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. the manufacturer identification is assigned by jedec, and has the value 20h for stmicroelectronics. the device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (80h), and the memory capacity of the device in the second byte (15h). any read identification (rdid) instruction while an erase or pr ogram cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. the device is first selected by driving chip select (s ) low. then, the 8-bit instruction code for the instruction is shifted in. this is follow ed by the 24-bit device identification, stored in the memory, being shifted out on serial data output (q), each bit being shifted out during the falling edge of serial clock (c). the instruction sequence is shown in figure 8 . the read identification (rdid) instruction is terminated by dr iving chip select (s ) high at any time during data output. when chip select (s ) is driven high, the device is put in the stand-by power mode. once in the stand-by power mode, the device waits to be selected, so that it can receive, decode and execute instructions. figure 8. read identification (rdid) instruction sequence and data-out sequence table 6. read identification (rdid) data-out sequence manufacturer identification device identification memory type memory capacity 20h 80h 15h c d s 2 1 3456789101112131415 instruction 0 ai06809b q manufacturer identification high impedance msb 15 1413 3210 device identification msb 16 17 18 28 29 30 31
m25pe16 instructions 25/56 6.4 read status register (rdsr) the read status register (rdsr) instruction allows the status register to be read. the status register may be read at any time, even while a program, erase or write cycle is in progress. when one of these cycles is in progre ss, it is recommended to check the write in progress (wip) bit before sending a new instruction to the device. it is also possible to read the status register continuously, as shown in figure 9 . the status bits of the status register are as follows: 6.4.1 wip bit the write in progress (wip) bit indicates whether the memory is busy with a write, program or erase cycle. when set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress. 6.4.2 wel bit the write enable latch (wel) bit indicates the status of the internal write enable latch. when set to 1 the internal write enable latch is set, when set to 0 the internal write enable latch is reset and no write, program or erase instruction is accepted. 6.4.3 bp2, bp1, bp0 bits the block protect (bp2, bp1, bp0) bits are non-volatile. they define the size of the area to be software protected against program and erase instructions. these bits are written with the write status register (wrsr) instruction. when one or more of the block protect (bp2, bp1, bp0) bits is set to 1, the relevant memory area (as defined in ta bl e 3 ) becomes protected against page program (pp), sector erase (se) and subsector erase (sse) instructions. the block protect (bp2, bp1, bp0) bits can be written provided that the hardware protected mode has not been set. the bulk erase (be) instruction is executed if, and only if: all block protect (bp2 , bp1, bp0) bits are 0 the lock register protection bits are not all set (?1?) 6.4.4 srwd bit the status register write disable (srwd) bit is operated in conjunction with the write protect (w ) signal. when the status register write disable (srwd) bit is set to 1, and write protect (w ) is driven low, the non-volatile bits of the status register (srwd, bp2, bp1, bp0) become read-only bits. in such a state, as the write status register (wrsr) instruction is no longer accepted for execution, the definition of the size of the write protected area cannot be further modified. table 7. status register format (1) (2) 1. wel (write enable latch) and wip ((write in program) are volatile read-only bits (wel is set and reset by specific instructions; wip is au tomatically set and reset by the internal logic of the device). 2. srwd = status register write protec t bit; bp0, bp1, bp2 = block protect bits. b7 b0 srwd 0 0 bp2 bp1 bp0 wel wip
instructions m25pe16 26/56 figure 9. read status register (rdsr) instruction sequence and data-out sequence c d s 2 1 3456789101112131415 instruction 0 ai02031e q 7 6543210 status register out high impedance msb 7 6543210 status register out msb 7
m25pe16 instructions 27/56 6.5 write status register (wrsr) the write status register (wrsr) instruction a llows new values to be written to the status register. before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded and executed, the device sets the write enable latch (wel). the write status register (wrsr) instruct ion is entered by driving chip select (s ) low, followed by the instruction code and the data byte on serial data input (d). the instruction sequence is shown in figure 10 . the write status register (wrsr) instruction has no effect on b6, b5, b1 and b0 of the status register. b6 and b5 are always read as 0. chip select (s ) must be driven high after the eighth bit of the data byte has been latched in. if not, the write status register (wrsr) instruction is not executed. as soon as chip select (s ) is driven high, the self-timed write stat us register cycle (whose duration is t w ) is initiated. while the write status register cycle is in progress , the status register may still be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed write status register cycle, and is 0 when it is completed. when the cycle is completed, the write enable latch (wel) is reset. the write status register (wrsr) instruction allows the user to change the values of the block protect (bp2, bp1, bp0) bits, to define the size of the area that is to be treated as read-only, as defined in ta b l e 3 . the write status register (wrsr) instruction also allows the user to set or reset the status register write disable (srwd) bit in accordance with the write protect (w ) signal (see section 6.4.4 ). if a write status register (wrsr) in struction is interrupted by a reset low pulse, the internal cycle of the write status register operation (whose duration is t w ) is first completed (provided that the supply voltage v cc remains within the operating range). after that the device enters the reset mode (see also table 12: device status after a reset low pulse and table 20: timings after a reset low pulse ). figure 10. write status register (wrsr) instruction sequence c d ai02282d s q 2 1 3456789101112131415 high impedance instruction status register in 0 765432 0 1 msb
instructions m25pe16 28/56 the protection features of the device are summarized in ta bl e 8 . when the status register write disable (srwd) bit of the status register is 0 (its initial delivery state), it is possible to write to the status register provided that the write enable latch (wel) bit has previously been set by a write enable (wren) in struction, regardless of the whether write protect (w ) is driven high or low. when the status register write disable (srwd) bit of the status register is set to 1, two cases need to be considered, depending on the state of write protect (w ): if write protect (w ) is driven high, it is possible to write to the status register provided that the write enable latch (wel) bit has previously been set by a write enable (wren) instruction. if write protect (w ) is driven low, it is not possible to write to the status register even if the write enable latch (wel) bit has previously been set by a write enable (wren) instruction. (attempts to write to the status register are rejected, and are not accepted for execution). as a consequence, all the data bytes in the memory area that are software protected (spm2) by the block pr otect (bp2, bp1, bp0) bi ts of the status register, are also hardware protected against data modification. regardless of the order of the two events, the hardware protected mode (hpm) can be entered: by setting the status register write disabl e (srwd) bit after driving write protect (w ) low or by driving write protect (w ) low after setting the status register write disable (srwd) bit. the only way to exit the hardware protected mode (hpm) once entered is to pull write protect (w ) high. if write protect (w ) is permanently tied high, the hardware protected mode (hpm) can never be activated, and only the software protected mode (spm2), using the block protect (bp2, bp1, bp0) bits of the status register, can be used. table 8. protection modes w signal srwd bit mode write protection of the status register memory content protected area (1) 1. as defined by the values in the block protect (bp2 , bp1, bp0) bits of the status register, as shown in table 3 . unprotected area (1) 10 second software protected (spm2) status register is writable (if the wren instruction has set the wel bit) the values in the srwd, bp2, bp1 and bp0 bits can be changed protected against page program, sector erase and bulk erase ready to accept page program and sector erase instructions 00 11 01 hardware protected (hpm) status register is hardware write protected the values in the srwd, bp2, bp1 and bp0 bits cannot be changed protected against page program, sector erase and bulk erase ready to accept page program and sector erase instructions
m25pe16 instructions 29/56 6.6 read data bytes (read) the device is first selected by driving chip select (s ) low. the instruction code for the read data bytes (read) instruction is followed by a 3-byte address (a23-a0), each bit being latched-in during the rising edge of serial clock (c). then the memory contents, at that address, is shifted out on serial data output (q), each bit being shifted out, at a maximum frequency f r , during the falling edge of serial clock (c). the instruction sequence is shown in figure 11 . the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. the whole memory can, therefore, be read with a single read data bytes (read) instruction. when the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. the read data bytes (read) instruction is terminated by driving chip select (s ) high. chip select (s ) can be driven high at any time during data output. any read data bytes (read) instruction, while an erase, program or write cycl e is in progress, is rejected without having any effects on the cycle that is in progress. figure 11. read data bytes (read) instruction sequence and data-out sequence 1. address bits a23 to a21 are don?t care. c d ai03748d s q 23 2 1 345678910 2829303132333435 2221 3210 36 37 38 76543 1 7 0 high impedance data out 1 instruction 24-bit address 0 msb msb 2 39 data out 2
instructions m25pe16 30/56 6.7 read data bytes at higher speed (fast_read) the device is first selected by driving chip select (s ) low. the instruction code for the read data bytes at higher speed (fas t_read) instruction is follow ed by a 3-byte address (a23- a0) and a dummy byte, each bit being latched-in during the rising edge of serial clock (c). then the memory contents, at that address, is shifted out on serial data output (q), each bit being shifted out, at a maximum frequency f c , during the falling edge of serial clock (c). the instruction sequence is shown in figure 12 . the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. the whole memory can, therefore, be read with a single read data bytes at higher speed (fast_read) instruction. when the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. the read data bytes at higher speed (fast_rea d) instruction is terminated by driving chip select (s ) high. chip select (s ) can be driven high at any time during data output. any read data bytes at higher speed (fast_read) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 12. read data bytes at higher speed (fast_read) instruction sequence and data-out sequence 1. address bits a23 to a21 are don?t care. c d ai04006 s q 23 2 1 345678910 28293031 2221 3210 high impedance instruction 24 bit address 0 c d s q 32 33 34 36 37 38 39 40 41 42 43 44 45 46 765432 0 1 data out 1 dummy byte msb 7 6543210 data out 2 msb msb 7 47 765432 0 1 35
m25pe16 instructions 31/56 6.8 read lock register (rdlr) the device is first selected by driving chip select (s ) low. the instruction code for the read lock register (rdlr) instruction is followed by a 3-byte address (a23-a0) pointing to any location inside the concerned sector. each address bit is latched-in during the rising edge of serial clock (c). then the value of the lock register is shifted out on serial data output (q), each bit being shifted out, at a maximum frequency f c , during the falling edge of serial clock (c). the instruction sequence is shown in figure 13 . the read lock register (rdl r) instruction is terminated by driving chip select (s ) high at any time during data output. any read lock register (rdlr) instruction, wh ile an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 13. read lock register (rdlr) instruction sequence and data-out sequence table 9. lock register out bit bit name value function b7-b2 reserved b1 sector lock down ?1? the write lock and lock down bits cannot be changed. once a ?1? is written to the lock down bit it cannot be cleared to ?0?, except by a reset or power-up. ?0? the write lock and lock down bits can be changed by writing new values to them. (default value). b0 sector write lock ?1? write, program and erase operations in this sector will not be executed. the memory contents will not be changed. ?0? write, program and erase operations in this sector are executed and will modify the sector contents. (default value). c d ai10783 s q 23 2 1 345678910 2829303132333435 2221 3210 36 37 38 76543 1 0 high impedance lock register out instruction 24-bit address 0 msb msb 2 39
instructions m25pe16 32/56 6.9 page write (pw) the page write (pw) instruction allows bytes to be written in the memory. before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the page write (pw) instruction is entered by driving chip select (s ) low, followed by the instruction code, three address bytes and at least one data byte on serial data input (d). the rest of the page remains unchanged if no power failure occurs during this write cycle. the page write (pw) instruction performs a page erase cycle even if only one byte is updated. if the 8 least significant address bits (a7-a0) are not all zero, all transmitted data exceeding the addressed page boundary roll over, and are written from the start address of the same page (the one whose 8 least significant address bits (a7-a0) are all zero). chip select (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 14 . if more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be written correctly within the same page. if less than 256 data bytes are sent to device, they are correctly written at the requested addresses without having any effects on the other bytes of the same page. for optimized timings, it is recommended to use the page write (pw) instruction to write all consecutive targeted bytes in a single sequence versus using several page write (pw) sequences with each containing only a few bytes chip select (s ) must be driven high after the eighth bit of the last data byte has been latched in, otherwise the page write (pw) instruction is not executed. as soon as chip select (s ) is driven high, the self-timed page write cycle (whose duration is t pw ) is initiated. while the page write cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed page write cycle, and is 0 when it is completed. at some unspecified time before the cycle is complete, the write enable latch (wel) bit is reset. a page write (pw) instruction applied to a page that is hardware or software protected is not executed. any page write (pw) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. if reset (reset ) is driven low while a page write (pw) cycle is in progress, the page write cycle is interrupted and the programmed data may be corrupted (see table 12: device status after a reset low pulse ). on reset going low, the device enters the reset mode and a time of t rhsl is then required before the device can be re-selected by driving chip select (s ) low. for the value of t rhsl see table 20: timings after a reset low pulse in section 11: dc and ac parameters .
m25pe16 instructions 33/56 figure 14. page write (pw) instruction sequence 1. address bits a23 to a21 are don?t care 2. 1 n 256 c d ai04045 s 42 41 43 44 45 46 47 48 49 50 52 53 54 55 40 c d s 23 2 1 345678910 2829303132333435 2221 3210 36 37 38 instruction 24-bit address 0 765432 0 1 data byte 1 39 51 765432 0 1 data byte 2 765432 0 1 data byte 3 data byte n 765432 0 1 msb msb msb msb msb
instructions m25pe16 34/56 6.10 page program (pp) the page program (pp) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0, only). before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the page program (pp) instruction is entered by driving chip select (s ) low, followed by the instruction code, three address bytes and at least one data byte on serial data input (d). if the 8 least significant address bits (a7-a0) are not all zero, all transmitted data exceeding the addressed page boundary roll over, and are programmed from the start address of the same page (the one whose 8 least significant address bits (a7-a0) are all zero). chip select (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 15 . if more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. if less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. for optimized timings, it is recommended to use the page program (pp) instruction to program all consecutive targeted bytes in a single sequence versus using several page program (pp) sequences with each containing only a few bytes (see ta b l e 1 8 : ac characteristics ). chip select (s ) must be driven high after the eighth bit of the last data byte has been latched in, otherwise the page program (pp) instruction is not executed. as soon as chip select (s ) is driven high, the self-timed page program cycle (whose duration is t pp ) is initiated. while the page program cy cle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed page progra m cycle, and is 0 when it is completed. at some unspecified time before the cycle is complete, the write enable latch (wel) bit is reset. a page program (pp) instruction applied to a page that is hardware or software protected is not executed. any page program (pp) instruction, while an eras e, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. if reset (reset ) is driven low while a page program (pp) cycle is in progress, the page program cycle is interrupted and the programmed data may be corrupted (see table 12: device status after a reset low pulse ). on reset going low, the device enters the reset mode and a time of t rhsl is then required before the device can be re-selected by driving chip select (s ) low. for the value of t rhsl see table 20: timings after a reset low pulse in section 11: dc and ac parameters .
m25pe16 instructions 35/56 figure 15. page program (pp) instruction sequence 1. address bits a23 to a21 are don?t care 2. 1 n 256 c d ai04044 s 42 41 43 44 45 46 47 48 49 50 52 53 54 55 40 c d s 23 2 1 345678910 2829303132333435 2221 3210 36 37 38 instruction 24-bit address 0 765432 0 1 data byte 1 39 51 765432 0 1 data byte 2 765432 0 1 data byte 3 data byte n 765432 0 1 msb msb msb msb msb
instructions m25pe16 36/56 6.11 write to lock register (wrlr) the write to lock register (wrlr) instruct ion allows bits to be changed in the lock registers. before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the write to lock register (wrlr) instruct ion is entered by driving chip select (s ) low, followed by the instruction code, three address bytes (pointing to any address in the targeted sector and one data byte on serial data input (d). the instruction sequence is shown in figure 16 . chip select (s ) must be driven high after the eighth bit of the data byte has been latched in, otherwise the write to lock register (wrlr) instruction is not executed. lock register bits are volatile, and therefore do not require time to be written. when the write to lock register (wrlr) instruction has been successfully executed, the write enable latch (wel) bit is reset after a delay time less than t shsl minimum value. any write to lock register (wrlr) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 16. write to lock register (wrlr) instruction sequence table 10. lock register in sector bit value all sectors b7-b2 ?0? b1 sector lock down bit value (refer to ta bl e 9 ) b0 sector write lock bit value (refer to ta bl e 9 ) ai10784 c d s 23 2 1 345678910 2829303132333435 2221 3210 36 37 38 instruction 24-bit address 0 765432 0 1 lock register in 39 msb msb
m25pe16 instructions 37/56 6.12 page erase (pe) the page erase (pe) instruction sets to 1 (ffh) all bits inside the chosen page. before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the page erase (pe) instruction is entered by driving chip select (s ) low, followed by the instruction code, and three address bytes on serial data input (d). any address inside the page is a valid address for the page er ase (pe) instructio n. chip select (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 17 . chip select (s ) must be driven high after the eighth bit of the last address byte has been latched in, otherwise the page erase (pe) instruction is not executed. as soon as chip select (s ) is driven high, the self-timed page erase cycle (whose duration is t pe ) is initiated. while the page erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self- timed page erase cycle, and is 0 when it is co mpleted. at some uns pecified time before the cycle is complete, the write enable latch (wel) bit is reset. a page erase (pe) instruction applied to a page that is hardware or software protected is not executed. any page erase (pe) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. if reset (reset ) is driven low while a page erase (pe) cycle is in progress, the page erase cycle is interrupted and the pr ogrammed data may be corrupted (see ta b l e 1 2 : device status after a reset low pulse ). on reset going low, the device enters the reset mode and a time of t rhsl is then required before the device can be re-selected by driving chip select (s ) low. for the value of t rhsl see table 20: timings after a reset low pulse in section 11: dc and ac parameters . figure 17. page erase (pe) instruction sequence 1. address bits a23 to a21 are don?t care. 24 bit address c d ai04046 s 2 1 3456789 293031 instruction 0 23 22 2 0 1 msb
instructions m25pe16 38/56 6.13 sector erase (se) the sector erase (se) instruction sets to 1 (ffh) all bits inside the chosen sector. before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the sector erase (se) instruction is entered by driving chip select (s ) low, followed by the instruction code, and three address bytes on serial data input (d). any address inside the sector (see ta b l e 4 ) is a valid address for the sector erase (se) instruction. chip select (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 18 . chip select (s ) must be driven high after the eighth bit of the last address byte has been latched in, otherwise the sector erase (se) instruction is not executed. as soon as chip select (s ) is driven high, the self-timed sector erase cycle (whose duration is t se ) is initiated. while the sector erase cycle is in pr ogress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed sector erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is complete, the write enable latch (wel) bit is reset. a sector erase (se) instruction applied to a sector that contains a page that is hardware or software protected is not executed. any sector erase (se) instructio n, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. if reset (reset ) is driven low while a sector erase (se) cycle is in progress, the sector erase cycle is interrupted and data may not be erased (see table 12: device status after a reset low pulse ). on reset going low, the device enters the reset mode and a time of t rhsl is then required before the device can be re-selected by driving chip select (s ) low. for the value of t rhsl see table 20: timings after a reset low pulse in section 11: dc and ac parameters . figure 18. sector erase (se) instruction sequence 1. address bits a23 to a21 are don?t care. 24 bit address c d ai03751d s 2 1 3456789 293031 instruction 0 23 22 2 0 1 msb
m25pe16 instructions 39/56 6.14 subsector erase (sse) the subsector erase (sse) instruction sets to 1 (ffh) all bits inside the chosen subsector. before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the subsector erase (se) instruction is entered by driving chip select (s ) low, followed by the instruction code, and three address bytes on serial data input (d). any address inside the subsector (see ta b l e 4 ) is a valid address for the subsector erase (se) instruction. chip select (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 18 . chip select (s ) must be driven high after the eighth bit of the last address byte has been latched in, otherwise the subsector erase (se) instruction is not executed. as soon as chip select (s ) is driven high, the self-timed subsector erase cycle (whose duration is t sse ) is initiated. while the subsector erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed subsector erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is complete, the write enable latch (wel) bit is reset. a subsector erase (sse) instruction applied to a subsector that contains a page that is hardware or software protected is not executed. any subsector erase (sse) inst ruction, while an erase, pr ogram or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. if reset (reset ) is driven low while a subsector er ase (sse) cycle is in progress, the subsector erase cycle is interrupted and data may not be erased correctly (see ta b l e 1 2 : device status after a reset low pulse ). on reset going low, the device enters the reset mode and a time of t rhsl is then required before the device can be re-selected by driving chip select (s ) low. for the value of t rhsl see table 20: timings after a reset low pulse in section 11: dc and ac parameters . figure 19. subs ector erase (sse) instruction sequence 1. address bits a23 to a21 are don?t care. 24 bit address c d ai12356 s 2 1 3456789 293031 instruction 0 23 22 20 1 msb
instructions m25pe16 40/56 6.15 bulk erase (be) the bulk erase (be) instruction sets all bits to 1 (ffh). before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the bulk erase (be) instruction is entered by driving chip select (s ) low, followed by the instruction code on serial da ta input (d). chip select (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 20 . chip select (s ) must be driven high after the eighth bit of the instruction code has been latched in, otherwise the bulk erase instruction is not executed. as soon as chip select (s ) is driven high, the self-timed bulk erase cycle (whose duration is t be ) is initiate d. while the bulk erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed bulk erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. any bulk erase (be) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. a bulk erase (be) instruction is ignored if at least one sector or subsector is write-protected (hardware or software protection). if reset (reset ) is driven low while a bulk erase (be) cycle is in progress, the bulk erase cycle is interrupted and data may not be erased correctly (see table 12: device status after a reset low pulse ). on reset going low, the device enters the reset mode and a time of t rhsl is then required before the device can be re-selected by driving chip select (s ) low. for the value of t rhsl see table 20: timings after a reset low pulse in section 11: dc and ac parameters . figure 20. bulk erase (be) instruction sequence c d ai03752d s 2 1 34567 0 instruction
m25pe16 instructions 41/56 6.16 deep power-down (dp) executing the deep power-down (dp) instruction is the only way to put the device in the lowest consumption mode (the deep power-down mode). it can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all write, program and erase instructions. driving chip select (s ) high deselects the device, and puts the device in the standby mode (if there is no internal cycle currently in prog ress). but this mode is not the deep power- down mode. the deep power-down mode can only be entered by executing the deep power-down (dp) instruction, subsequently reducing the standby current (from i cc1 to i cc2 , as specified in ta b l e 1 7 ). once the device has entered the deep power-down mode, all instructions are ignored except the release from deep power-down (rdp) instruction. issuing the release from deep power-down (rdp) instruction will cause the device to exit the deep power-down mode. the deep power-down mode automatically stops at power-down, and the device always powers-up in the standby mode. the deep power-down (dp) instruction is entered by driving chip select (s ) low, followed by the instruction code on serial data input (d). chip select (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 21 . chip select (s ) must be driven high after the eighth bit of the instruction code has been latched in, otherwise the deep power-down (dp) instruction is not executed. as soon as chip select (s ) is driven high, it requires a delay of t dp before the supply current is reduced to i cc2 and the deep power-down mode is entered. any deep power-down (dp) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 21. deep power-down (dp) instruction sequence c d ai03753d s 2 1 34567 0 t dp deep power-down mode stand-by mode instruction
instructions m25pe16 42/56 6.17 release from deep power-down (rdp) once the device has entered the deep power-down mode, all instructions are ignored except the release from deep power-down (rdp ) instruction. executing this instruction takes the device out of the deep power-down mode. the release from deep power-down (rdp) instruction is entered by driving chip select (s ) low, followed by the instruction code on serial data input (d). chip select (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 22 . the release from deep power-do wn (rdp) instruction is termin ated by driving chip select (s ) high. sending additional clock cycles on serial clock (c), while chip select (s ) is driven low, cause the instruction to be rejected, and not executed. after chip select (s ) has been driven high, followed by a delay, t rdp , the device is put in the standby mode. chip select (s ) must remain high at least until this period is over. the device waits to be selected, so that it can receive, decode and execute instructions. any release from deep power-down (rdp) instru ction, while an erase, program or write cycle is in progress, is reject ed without having any effects on the cycle that is in progress. figure 22. release from deep power-down (rdp) instruction sequence c d ai06807 s 2 1 34567 0 t rdp stand-by mode deep power-down mode q high impedance instruction
m25pe16 power-up and power-down 43/56 7 power-up and power-down at power-up and power-down, the device must not be selected (that is chip select (s ) must follow the voltage applied on v cc ) until v cc reaches the correct value: v cc (min) at power-up, and then for a further delay of t vsl v ss at power-down a safe configuration is provided in section 3: spi modes . to avoid data corruption and inadvertent write operations during power-up, a power on reset (por) circuit is included. the logic inside the device is held reset while v cc is less than the power on reset (por) threshold voltage, v wi ? all operations are disabled, and the device does not resp ond to any instruction. moreover, the device ignores all write enable (wren), page write (pw), page program (pp), page erase (pe), sector erase (se), su bsector erase (sse), bulk erase (be), write status register (wrsr) and write to lock regi ster (wrlr) instructio ns until a time delay of t puw has elapsed after the moment that v cc rises above the v wi threshold. however, the correct operation of the device is not guaranteed if, by this time, v cc is still below v cc (min). no write, program or erase instructions should be sent until the later of: t puw after v cc passed the v wi threshold t vsl after v cc passed the v cc (min) level these values are specified in ta bl e 1 1 . if the delay, t vsl , has elapsed, after v cc has risen above v cc (min), the device can be selected for read instructions even if the t puw delay is not yet fully elapsed. as an extra protec tion, the reset (reset ) signal could be driven low for the whole duration of the power-up and power-down phases. at power-up, the device is in the following state: the device is in the standby mode (not the deep power-down mode). the write enable latch (wel) bit is reset. the write in progress (wip) bit is reset the lock registers are reset (write lock bit, lock down bit) = (0, 0) normal precautions must be taken for su pply rail decoupling, to stabilize the v cc supply. each device in a system should have the v cc line decoupled by a suitable capacitor close to the package pins. (generally, this capacitor is of the order of 100 nf). at power-down, when v cc drops from the operating voltage, to below the power on reset (por) threshold voltage, v wi , all operations are disabled and the device does not respond to any instruction. (the designer needs to be aware that if a power-down occurs while a write, program or erase cycle is in progress, some data corruption can result.)
power-up and power-down m25pe16 44/56 figure 23. power-up timing table 11. power-up timing and v wi threshold symbol parameter min. max. unit t vsl (1) 1. these parameters are char acterized only, over the te mperature range ?40c to +85c. v cc (min) to s low 30 s t puw (1) time delay before the first write, program or erase instruction 1 10 ms v wi (1) write inhibit voltage 1.5 2.5 v v cc ai04009c v cc (min) v wi reset state of the device chip selection not allowed program, erase and write commands are rejected by the device tvsl tpuw time read access allowed device fully accessible v cc (max)
m25pe16 reset 45/56 8 reset driving reset (reset ) low while an internal operation is in progress will affect this operation (write, program or erase cycle) and data may be lost. all the lock bits are reset to 0 after a reset low pulse. ta bl e 1 2 shows the status of the device after a reset low pulse. 9 initial delivery state the device is delivered with the memory arra y erased: all bits are set to 1 (each byte contains ffh). all usable status register bits are 0. table 12. device status after a reset low pulse conditions: reset pulse occurred lock bits status internal logic status addressed data while decoding an instruction (1) : wren, wrdi, rdid, rdsr, read, rdlr, fast_read, wrlr, pw, pp, pe, se, be, sse, dp, rdp 1. s remains low while reset is low. reset to 0 same as por not significant under completion of an erase or program cycle of a pw, pp, pe, sse, se, be operation reset to 0 equivalent to por addressed data could be modified under completion of a wrsr operation reset to 0 equivalent to por (after t w ) write is correctly completed device deselected (s high) and in standby mode reset to 0 same as por not significant
maximum rating m25pe16 46/56 10 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. table 13. absolute maximum ratings symbol parameter min. max. unit t stg storage temperature ?65 150 c t lead lead temperature during soldering see (1) 1. compliant with jedec std j-std- 020c (for small body, sn-pb or pb assembly), the st ecopack? 7191395 specification, and the european directive on re strictions on hazardous substances (rohs) 2002/95/eu. v io input and output voltage (with respect to ground) ?0.6 v cc + 0.6 v v cc supply voltage ?0.6 4.0 v v esd electrostatic discharge voltage (human body model) (2) 2. jedec std jesd22-a114a (c1=100 pf, r1=1500 ? , r2=500 ? ). ?2000 2000 v
m25pe16 dc and ac parameters 47/56 11 dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. 1. output hi-z is defined as the point where data out is no longer driven. figure 24. ac measurement i/o waveform table 14. operating conditions symbol parameter min. max. unit v cc supply voltage 2.7 3.6 v t a ambient operating temperature ?40 85 c table 15. ac measurement conditions symbol parameter min. max. unit c l load capacitance 30 pf input rise and fall times 5 ns input pulse voltages 0.2v cc to 0.8v cc v input and output timing reference voltages 0.3v cc to 0.7v cc v table 16. capacitance (1) 1. sampled only, not 100% tested, at t a =25c and a frequency of 20 mhz. symbol parameter test condition min . max . unit c out output capacitance (q) v out = 0v 8 pf c in input capacitance (other pins) v in = 0v 6 pf ai00825b 0.8v cc 0.2v cc 0.7v cc 0.3v cc input and output timing reference levels input levels
dc and ac parameters m25pe16 48/56 table 17. dc characteristics symbol parameter test condition (in addition to those in ta b l e 1 4 ) min. max. unit i li input leakage current 2 a i lo output leakage current 2 a i cc1 standby current (standby and reset modes) s = v cc , v in = v ss or v cc 50 a i cc2 deep power-down current s = v cc , v in = v ss or v cc 10 a i cc3 operating current (fast_read) c = 0.1v cc / 0.9.v cc at 50mhz, q = open 8ma i cc4 operating current (pw) s = v cc 15 ma i cc5 operating current (se) s = v cc 15 ma i cc6 operating current (wrsr) s = v cc 15 ma v il input low voltage ? 0.5 0.3v cc v v ih input high voltage 0.7v cc v cc +0.4 v v ol output low voltage i ol = 1.6 ma 0.4 v v oh output high voltage i oh = ?100 av cc ?0.2 v
m25pe16 dc and ac parameters 49/56 table 18. ac characteristics test conditions specified in ta bl e 1 4 and ta b l e 1 5 symbol alt. parameter min. typ. max. unit f c f c clock frequency for the following instructions: fast_read, rdlr, pw, pp, wrlr, pe, se, sse, dp, rdp, wren, wrdi, rdsr, wrsr d.c. 50 mhz f r clock frequency for read instructions d.c. 33 mhz t ch (1) t clh clock high time 9 ns t cl (1) t cll clock low time 9 ns clock slew rate 2 (peak to peak) 0.1 v/ns t slch t css s active setup time (relative to c) 5 ns t chsl s not active hold time (relative to c) 5 ns t dvch t dsu data in setup time 2 ns t chdx t dh data in hold time 5 ns t chsh s active hold time (relative to c) 5 ns t shch s not active setup time (relative to c) 5 ns t shsl t csh s deselect time 100 ns t shqz (2) t dis output disable time 8 ns t clqv t v clock low to output valid 8 ns t clqx t ho output hold time 0 ns t whsl (3) write protect setup time 50 ns t shwl (3) write protect hold time 100 ns t dp (2) s to deep power-down 3 s t rdp (2) s high to standby mode 30 s t w write status register cycle time 3 15 ms t pw (4) page write cycle time (256 bytes) 11 23 ms t pp (4) page program cycle time (256 bytes) 0.8 3ms page program cycle time (n bytes) int(n/8) 0.025 (5) t pe page erase cycle time 10 20 ms t se sector erase cycle time 1 5 s t sse subsector erase cycle time 40 150 ms t be bulk erase cycle time 17 60 s 1. t ch + t cl must be greater than or equal to 1/ f c 2. value guaranteed by characterization, not 100% tested in production. 3. only applicable as a constraint for a wr sr instruction when srwd is set at 1. 4. when using pp and pw instructions to update consecutive bytes, optimized timings are obtained with one sequence including all the bytes versus severa l sequences of only a few bytes (1 n 256). 5. int(a) corresponds to the upper integer part of a. e.g. int(12/8) = 2, int(32/8) = 4 int(15.3) =16.
dc and ac parameters m25pe16 50/56 figure 25. serial input timing figure 26. write protect setup and hold timing figure 27. output timing c d ai01447c s msb in q tdvch high impedance lsb in tslch tchdx tchcl tclch tshch tshsl tchsh tchsl c d s q high impedance w twhsl tshwl ai12357c c q ai01449e s lsb out d addr.lsb in tshqz tch tcl tqlqh tqhql tclqx tclqv tclqx tclqv
m25pe16 dc and ac parameters 51/56 figure 28. reset ac waveforms while a program or erase cycle is in progress table 19. reset conditions test conditions specified in ta bl e 1 4 and ta bl e 1 5 symbol alt. parameter conditions min. typ. max. unit t rlrh (1) 1. value guaranteed by characterizati on, not 100% tested in production. t rst reset pulse width 10 s t shrh chip select high to reset high chip should have been deselected before reset is de-asserted 10 ns table 20. timings after a reset low pulse (1)(2) 1. all the values are guaranteed by characte rization, and not 100% tested in production. 2. see table 12 for a description of the device status after a reset low pulse. test conditions specified in ta bl e 1 4 and ta b l e 1 5 symbol alt. parameter conditions: reset pulse occurred min. typ. max. unit t rhsl t rec reset recovery time while decoding an instruction (3) : wren, wrdi, rdid, rdsr, read, rdlr, fast_read, wrlr, pw, pp, pe, se, be, sse, dp, rdp 3. s remains low while reset is low. 30 s under completion of an erase or program cycle of a pw, pp, pe, se, be operation 300 s under completion of an erase cycle of an sse operation 3ms under completion of a wrsr operation t w (see ta bl e 1 8 ) ms device deselected (s high) and in standby mode 0s ai06808b reset trlrh s trhsl tshrh
package mechanical m25pe16 52/56 12 package mechanical figure 29. vfqfpn8 (mlp8) 8-lead very thin dual flat package no lead, 6 5mm, package outline 1. drawing is not to scale. 2. the circle in the top view of the package indicates the position of pin 1. table 21. vfqfpn8 (mlp8) 8-lead very thin fine pitch quad flat package no lead, 6 5 mm, package mechanical data symbol millimeters inches typ min max typ min max a 0.85 0.80 1.00 0.0335 0.0315 0.0394 a1 0.00 0.05 0.0000 0.0020 a2 0.65 0.0256 a3 0.20 0.0079 b 0.40 0.35 0.48 0.0157 0.0138 0.0189 d 6.00 0.2362 d1 5.75 0.2264 d2 3.40 3.20 3.60 0.1339 0.1260 0.1417 e 5.00 0.1969 e1 4.75 0.1870 e2 4.00 3.80 4.30 0.1575 0.1496 0.1693 e1.27? ?0.0500? ? r1 0.10 0.00 0.0039 0.0000 l 0.60 0.50 0.75 0.0236 0.0197 0.0295 12 12 aaa 0.15 0.0059 bbb 0.10 0.0039 ddd 0.05 0.0020 d e 70-me a2 a a3 a1 e1 d1 e e2 d2 l b r1 ddd bbb c cab aaa ca a b aaa cb m 0.10 ca 0.10 cb 2x
m25pe16 package mechanical 53/56 figure 30. so8 wide ? 8 lead plastic small outline, 208 mils body width, package outline 1. drawing is not to scale. 2. the circle in the top view of the package indicates the position of pin 1. table 22. so8 wide ? 8 lead plastic small outline, 208 mils body width, mechanical data symbol millimeters inches typ min max typ min max a2.500.098 a1 0.00 0.25 0.000 0.010 a2 1.51 2.00 0.059 0.079 b 0.40 0.35 0.51 0.016 0.014 0.020 c 0.20 0.10 0.35 0.008 0.004 0.014 cp 0.10 0.004 d6.050.238 e 5.02 6.22 0.198 0.245 e1 7.62 8.89 0.300 0.350 e1.27? ?0.050? ? k 0 10 0 10 l 0.50 0.80 0.020 0.031 n8 8 6l_me e n cp b e a2 d c l a1 k e1 a 1
part numbering m25pe16 54/56 13 part numbering for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. the category of second-level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. table 23. ordering information scheme example: m25pe16 ? v mp 6 t p device type m25pe = page-erasable serial flash memory device function 16 = 16 mbit (2mb x 8) operating voltage v = v cc = 2.7 v to 3.6 v package mw = so8 (208 mils width) mp = vfqfpn8 6x5mm (mlp8) device grade 6 = industrial: device tested with standard test flow over ?40 to 85 c option blank = standard packing t = tape and reel packing plating technology p or g = ecopack? (rohs compliant)
m25pe16 revision history 55/56 14 revision history table 24. document revision history date revision changes 16-feb-2006 0.1 initial release. 07-aug-2006 1 figure 3: bus master and memory devices on the spi bus updated and note 2 added. section 4.8.1: protocol-related protections clarified. address range for subsector 15 of sector 0 modified in ta b l e 4 : memory organization . reset signal behavior clarified in section 6.5: write status register (wrsr) , section 6.9: page write (pw) , section 6.10: page program (pp) , section 6.12: page erase (pe) , section 6.14: subsector erase (sse) , section 6.15: bulk erase (be) . section 8: reset added to describe the devi ce status after a reset low pulse. table reset while a read, program or erase cycle is in progres replaced by table 20: timings after a reset low pulse ta bl e 1 9 split into two tables (see also ta b l e 1 9 ). t be typical value updated. small text changes. 13-oct-2006 2 hpm2 specified in hpm1 and hpm2 paragraph. small text changes. table 12: device status after a reset low pulse modified. v io max. modified in table 13: absolute maximum ratings . f r , t w , t pw , t pp and t sse modified in table 18: ac characteristics . 20-nov-2006 3 tsl /w signal renamed as w , top sector lock functionality removed, hpm2 removed. paragraph added in section 3: spi modes . t lead added to ta bl e 1 3 : absolute maximum ratings . t thsl and t shtl timings removed from table 18: ac characteristics and figure 26: write protect setup and hold timing . so8w package specifications updated (see ta bl e 2 2 and figure 30 ). 12-apr-2007 4 document status promot ed from preliminary data to full datasheet. v cc supply voltage and v ss ground added. figure 3: bus master and memory devices on the spi bus updated, note 2 removed and replaced by an explanatory paragraph. behavior of wip bit and lock registers specified at power-up in section 7: power-up and power-down . vfqfpn8 package specific ations updated (see figure 29 and ta bl e 2 1 ).
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